Part Number Hot Search : 
D5V0S 13FAD STV2310D IS61LV ANP21F9H B90N6T YM3292 WE331
Product Description
Full Text Search
 

To Download NTY100N10 Datasheet File

  If you can't view the Datasheet, Please click here to try to view without PDF Reader .  
 
 


  Datasheet File OCR Text:
 NTY100N10
Preferred Device
Power MOSFET 123 A, 100 V N-Channel Enhancement-Mode TO264 Package
http://onsemi.com Features
* Source-to-Drain Diode Recovery Time Comparable to a Discrete * * *
Fast Recovery Diode Avalanche Energy Specified IDSS and RDS(on) Specified at Elevated Temperature Pb-Free Package is Available*
123 A, 100 V 9 mW @ VGS = 10 V (Typ)
N-Channel D
Applications
* PWM Motor Control * Power Supplies * Converters
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Rating Drain-Source Voltage Drain-Gate Voltage (RGS = 1 MW) Gate-Source Voltage - Continuous - Non-Repetitive (tp v 10 ms) Drain Current (Note 1) - Continuous @ TC = 25C - Pulsed Total Power Dissipation (Note 1) Derate above 25C Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 80 Vdc, VGS = 10 Vdc, Peak IL = 100 Apk, L = 0.1 mH, RG = 25 W) Thermal Resistance - Junction to Case - Junction to Ambient Symbol VDSS VDGR VGS VGSM ID Value 100 100 $ 20 $ 40 123 369 313 2.5 -55 to 150 500 Unit V V V V A A Watts W/C C mJ
G S
MARKING DIAGRAM & PIN ASSIGNMENT
1
NTY100N10 AYYWWG 2 3 TO-264 CASE 340G STYLE 1
IDM PD TJ, Tstg EAS
1 G
2 D
3 S
A YY WW G
= Assembly Location = Year = Work Week = Pb-Free Package
RqJC RqJA TL
0.4 25 260
C/W C
ORDERING INFORMATION
Device NTY100N10 NTY100N10G Package TO-264 TO-264 (Pb-Free) Shipping 25 Units/Rail 25 Units/Rail
Maximum Lead Temperature for Soldering Purposes, 0.125 in from case for 10 seconds
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Pulse Test: Pulse Width = 10 ms, Duty-Cycle = 2%.
Preferred devices are recommended choices for future use and best overall value.
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
(c) Semiconductor Components Industries, LLC, 2006
March, 2006 - Rev. 2
1
Publication Order Number: NTY100N10/D
NTY100N10
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS Drain-Source Breakdown Voltage (VGS = 0, ID = 250 mA) (Positive Temperature Coefficient) Zero Gate Voltage Drain Current (VGS = 0 Vdc, VDS = 100 Vdc, TJ = 25C) (VGS = 0 Vdc, VDS = 100 Vdc, TJ = 150C) Gate-Body Leakage Current (VGS = $20 Vdc, VDS = 0) ON CHARACTERISTICS (Note 2) Gate Threshold Voltage (VDS = VGS, ID = 250 mAdc) (Negative Temperature Coefficient) Static Drain-Source On-State Resistance (VGS = 10 Vdc, ID = 50 Adc) (VGS = 10 Vdc, ID = 50 Adc, 150C) Drain-Source On-Voltage (VGS = 10 Vdc, ID = 100 Adc) Forward Transconductance (VDS = 6 Vdc, ID = 50 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Notes 2, 3) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Total Gate Charge Gate-Source Charge (VDS = 80 Vdc, ID = 100 Adc, VGS = 10 Vdc) (VDD = 50 Vdc, ID = 100 Adc, VGS = 10 Vdc, RG = 9.1 W) td(on) tr td(off) tf QT Q1 Q2 Q3 BODY-DRAIN DIODE RATINGS (Note 2) Forward On-Voltage (IS = 100 Adc, VGS = 0 Vdc) (IS = 100 Adc, VGS = 0 Vdc, TJ = 150C) Reverse Recovery Time (IS = 100 Adc, VGS = 0 Vdc, dIS/dt = 100 A/ms) VSD - - - - - - 1.02 0.94 210 155 55 1.08 1.1 - - - - - mC Vdc - - - - - - - - 30 150 340 250 200 40 100 86 55 265 595 435 350 - - - nC ns (VDS = 25 Vdc, VGS = 0 Vdc, f = 1 MHz) Ciss Coss Crss - - - 7225 1800 270 10110 2540 540 pF VGS(th) 2.0 - - - - - 3.1 10.6 0.009 0.019 0.8 73 4.0 - 0.010 0.021 1.0 - Vdc mV/C W V(BR)DSS 100 - - - - - 144 - - - - - 10 100 100 Vdc mV/C mAdc Symbol Min Typ Max Unit
IDSS
IGSS
nAdc
RDS(on)
VDS(on) gFS
Vdc Mhos
trr ta tb QRR
ns
Reverse Recovery Stored Charge 2. Indicates Pulse Test: Pulse Width v300 ms max, Duty Cycle = 2%. 3. Switching characteristics are independent of operating junction temperature.
http://onsemi.com
2
NTY100N10
200 V = 10 V VGS = 9.0 V GS TJ = 25C VGS = 8.0 V VGS = 6.0 V VGS = 7.0 V VGS = 6.5 V 100 200 VDS w 10 V
ID, DRAIN CURRENT (A)
150
ID, DRAIN CURRENT (A)
150
VGS = 5.6 V
100
50
VGS = 5.0 V VGS = 4.6 V
50 TJ = 100C 0
TJ = 25C TJ = -55C 6 8 10
0 0 2 4 6 8 10 VDS, DRAIN-TO-SOURCE VOLTAGE (V)
0
2
4
VGS, GATE-TO-SOURCE VOLTAGE (V)
Figure 1. On-Region Characteristics
Figure 2. On-Region Characteristics
RDS(on), DRAIN-TO-SOURCE CURRENT (W)
0.018 0.016 0.014 0.012 0.01 0.008 0.006 0.004 0.002 0 0
RDS(on), DRAIN-TO-SOURCE RESISTANCE (W)
VGS = 10 V T = 100C
0.0095
T = 25C
0.009 VGS = 10 V 0.0085 VGS = 15 V
T = 25C
T = -55C
0.008
50
100
150
200
0.0075
0
50
100
150
20
ID, DRAIN CURRENT (A)
ID, DRAIN CURRENT (A)
Figure 3. On-Resistance versus Drain Current and Temperature
RDS(on), DRAIN-TO-SOURCE RESISTANCE (NORMALIZED) 2.5 2.0 1.5 1.0 0.5 0 -50 1000000 100000 IDSS, LEAKAGE (nA) 10000 1000 100 10 1.0 -25 0 25 50 75 100 125 150 0
Figure 4. On-Resistance versus Drain Current and Gate Voltage
ID = 50 A VGS = 10 V
VGS = 0 V
TJ = 125C TJ = 100C
20
40
60
80
100
TJ, JUNCTION TEMPERATURE (C)
VDS, DRAIN-TO-SOURCE VOLTAGE (V)
Figure 5. On-Resistance Variation with Temperature
Figure 6. Drain-to-Source Leakage Current versus Voltage
http://onsemi.com
3
NTY100N10
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (Dt) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.
http://onsemi.com
4
NTY100N10
20000 16000 12000 Crss 8000 4000 0 Ciss VDS = 0 Ciss VGS = 0 TJ = 25C
C, CAPACITANCE (pF)
Coss 10 5 Vgs 0 Vds 5 10 15 20 25
Figure 7. Capacitance Variation
10 8.0 6.0 4.0 2.0 0 0 Q3
QT VDS Q1 Q2 VGS
100 80 60 40 20
IDS =100 A TJ = 25C 50 100 150 Qg, TOTAL GATE CHARGE (nC)
0 200
Figure 8. Gate-to-Source and Drain-to-Source Voltage versus Total Charge
10000
1000 t, TIME (nC)
td(off) 100 tf tr td(on)
IS, SOURCE CURRENT (A)
VDD = 50 V ID = 100 A VGS = 10 V
100 80 60 40 20 0
VGS = 0 V TJ = 25C
10
1.0
1
10 RG, GATE RESISTANCE (W)
100
0
0.2
0.4
VDS, DRAIN-TO-SOURCE VOLTAGE (V) 0.6
VGS, GATE-TO-SOURCE VOLTAGE (V)
0.8
1
VSD, SOURCE-TO-DRAIN VOLTAGE (V)
Figure 9. Resistive Switching Time Variation versus Gate Resistance
Figure 10. Diode Forward Voltage versus Current
http://onsemi.com
5
NTY100N10
SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance-General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 ms. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RqJC). A Power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For
EAS, SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ)
reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain-to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.
1000 ID, DRAIN CURRENT (A) 100 10 10 ms 1 0.1 0.01 VGS = 20 V Single Pulse TC = 25C 0.1 1 100 ms 1 ms 10 ms Thermal Limit 10 dc 100 RDS(on) Limit Package Limit
500 ID = 100 A 400 300 200 100 0 25 50 75 100 125 150 TJ, STARTING JUNCTION TEMPERATURE (C)
1000
VDS, DRAIN-TO-SOURCE VOLTAGE (V)
Figure 11. Maximum Rated Forward Bias Safe Operating Area
Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature
http://onsemi.com
6
NTY100N10
SAFE OPERATING AREA
r (t) EFFECTIVE TRANSIENT THERMAL RESISTANC , (NORMALIZED)
1 D = 0.5 0.2 0.1 0.05 0.02 0.01 SINGLE PULSE t2 DUTY CYCLE, D = t1/t2 1.0E-03 1.0E-02 t, TIME (s) t1 P(pk)
0.1
RqJC(t) = r(t) RqJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RqJC(t)
0.01 1.0E-05
1.0E-04
1.0E-01
1.0E+00
1.0E+01
Figure 13. Thermal Response
di/ dt trr ta tb TIME tp IS 0.25 IS
IS
Figure 14. Diode Reverse Recovery Waveform
http://onsemi.com
7
NTY100N10
PACKAGE DIMENSIONS
TO-3BPL (TO-264) CASE 340G-02 ISSUE J
Q -B- U A R
1 2 3
0.25 (0.010)
M
TB
M
-T- C E
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. MILLIMETERS MIN MAX 28.0 29.0 19.3 20.3 4.7 5.3 0.93 1.48 1.9 2.1 2.2 2.4 5.45 BSC 2.6 3.0 0.43 0.78 17.6 18.8 11.2 REF 4.35 REF 2.2 2.6 3.1 3.5 2.25 REF 6.3 REF 2.8 3.2 INCHES MIN MAX 1.102 1.142 0.760 0.800 0.185 0.209 0.037 0.058 0.075 0.083 0.087 0.102 0.215 BSC 0.102 0.118 0.017 0.031 0.693 0.740 0.411 REF 0.172 REF 0.087 0.102 0.122 0.137 0.089 REF 0.248 REF 0.110 0.125
N
L P
K
F 2 PL
W G D 3 PL 0.25 (0.010)
M
J H TB
S
DIM A B C D E F G H J K L N P Q R U W
STYLE 1: PIN 1. GATE 2. DRAIN 3. SOURCE
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: N. American Technical Support: 800-282-9855 Toll Free Literature Distribution Center for ON Semiconductor USA/Canada P.O. Box 61312, Phoenix, Arizona 85082-1312 USA Phone: 480-829-7710 or 800-344-3860 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2-9-1 Kamimeguro, Meguro-ku, Tokyo, Japan 153-0051 Fax: 480-829-7709 or 800-344-3867 Toll Free USA/Canada Phone: 81-3-5773-3850 Email: orderlit@onsemi.com ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative.
http://onsemi.com
8
NTY100N10/D


▲Up To Search▲   

 
Price & Availability of NTY100N10

All Rights Reserved © IC-ON-LINE 2003 - 2022  

[Add Bookmark] [Contact Us] [Link exchange] [Privacy policy]
Mirror Sites :  [www.datasheet.hk]   [www.maxim4u.com]  [www.ic-on-line.cn] [www.ic-on-line.com] [www.ic-on-line.net] [www.alldatasheet.com.cn] [www.gdcy.com]  [www.gdcy.net]


 . . . . .
  We use cookies to deliver the best possible web experience and assist with our advertising efforts. By continuing to use this site, you consent to the use of cookies. For more information on cookies, please take a look at our Privacy Policy. X